The present disclosure relates to semiconductor structures, and particularly to a borderless contact structure for extremely thin semiconductor-on-insulator (ETSOI) devices and methods of manufacturing the same.
Extremely thin semiconductor-on-insulator (ETSOI) devices refer to semiconductor devices formed on an extremely thin semiconductor-on-insulator (ETSOI) substrate. A typical ETSOI substrate has a top semiconductor layer, which is also referred to as an extremely thin semiconductor-on-insulator (ETSOI) layer, having a thickness from 5 nm to 50 nm. A buried insulator layer provided underneath the top semiconductor layer has a thickness from 10 nm to 100 nm. An ETSOI substrate can be employed to form various semiconductor devices that derive performance advantage through the reduced thickness of the top semiconductor layer and/or the reduced thickness of the buried insulator layer compared with normal semiconductor-on-insulator (SOI) substrate.
For example, the reduction in the thickness of the top semiconductor layer provides full depletion of the channel, thereby enhancing the electrical control of the channel by the gate electrode and reducing the leakage current in a field effect transistor. Further, the reduction in the thickness of the buried insulator layer can enhance control by a back gate electrode in back-gated field effect transistors.
While ETSOI devices, and especially ETSOI field effect transistors (FETs), are promising candidates for advanced high performance devices, several manufacturing issues need to be resolved before ETSOI devices can be manufactured with high yield. One such issue is formation of divots around and/or over shallow trench isolation structures that are employed to provide lateral electrical isolation between adjacent devices. Specifically, etch steps and/or cleaning steps are repeatedly employed to recess various material layers and/or to clean surfaces before further processing. Divots are formed around shallow trench isolation structures during such etch steps and/or cleaning steps. For example, silicon oxide-based shallow trench isolation structures are susceptible to HF-based etches that can be employed to preclean semiconductor surfaces before epitaxy or formation of a gate dielectric.
Divots formed during such etch steps and/or cleaning steps can extend to a bottom semiconductor layer located underneath the buried insulator layer. The divots can be filled with a conductive material during formation of contact via structures, and a direct electrical short can be formed to the bottom semiconductor layer by the conductive material that is deposited in the divots as an extension of the contact via structures. Even if a direct electrical short is avoided, a conductive material deposited in divots can lead to an unacceptable level of leakage current between a portion of the bottom semiconductor layer and an electrical node that should be electrically isolated from the bottom semiconductor layer.